Programming with Transactional Memory

Title: Programming with Transactional Memory
Speaker: Dr. Bratin Saha （Programming Systems Lab, Intel）
Time: 4：00pm, Monday Dec. 10
Venue: Lecture room, Lab for Computer Science, Level 3 Building #5, Institute of Software, CAS

Abstract:Processor vendors have turned to chip-level multiprocessing (CMP) for increasing processor performance. This will force mainstream programmers to deal with parallelism. One of the pressing problems in parallel programming is synchronizing accesses to shared data. Traditionally, this has been done through mutual-exclusion locks, but lock-based synchronization suffers from several pitfalls such as deadlock, lack of composition, conservative locking, etc. In this talk, I will present transactional memory — an alternative concurrency control mechanism that eliminates many of the problems associated with lock-based synchronization. I will first discuss the language extensions, and the compiler and runtime support required for providing programmers access to transactional memory. I will use the Intel prototype C/C++ software transactional memory implementation to illustrate this. I will then discuss the HW primitives that can improve the performance of transactional memory implementations.

Bio:
Bratin Saha is a senior staff researcher in Intel’s Programming Systems Lab. He is one of the architects of locking and synchronization in Nehalem – Intel’s next generation processor. He is also one of the principal authors of the Intel 64 architecture memory ordering, which specifies the memory ordering for IA-32 and EM64T processors. He has more than 30 patents filed, and has published more than 20 papers in the leading conferences and journals. One of his papers was selected among the 25 seminal publications in intrusion tolerance and was published by IEEE in a special volume “Foundations of Intrusion Tolerant Systems”. Another paper was nominated for the best paper award in the International Symposium on Microarchitecture (MICRO 2006). His current research is focused on the design and implementation of modern concurrency abstractions such as transactional memory. He is one of the principal architects and implementers of the Intel prototype C/C++ software transactional memory implementation, as well as an (as yet) internal Java software transactional memory implementation. Bratin received his M.S. and Ph.D degrees in Computer Science from Yale University, and his BTech(B.S.) degree in Computer Science and Engineering from the
Indian Institute of Technology, Kharagpur.