Hard-Real-Time Scheduling on a Weakly Programmable Multi-core Processor with Application to Multi-standard Channel Decoding
Title: Hard-Real-Time Scheduling on a Weakly Programmable Multi-core Processor with Application to Multi-standard Channel Decoding
Speaker: Wei Tong (Eindhoven University of Technology)
Time: 14:30, Friday, April 20, 2012
Venue: Lecture room, 3rd Floor, Building 5#, State Key Laboratory of Computer Science, Institute of Software, Chinese Academy of Sciences|
Abstract: In Software Defined Radio (SDR), some or all of the physical layer functions are implemented by software. In this paper, we focus on the channel decoding part of SDR. We use Synchronous Data Flow (SDF) and Cyclo-Static Data Flow (CSDF) graphs to model channel decoding functions. We want to tackle the problem of scheduling a dynamic mix of multiple radios with throughput constraints on a multi-standard multi-channel channel decoder. The decoder consists of a Micro-Controller Unit (MCU) and several weakly programmable Hardware Units (HU) with internal states and very limited buffer sizes. Each HU has a Round Robin (RR) scheduler hosted on the MCU.
To reduce scheduling overhead, RR schedules applications at coarse granularity. Due to limited buffer sizes, some tasks of an application are tightly coupled. We propose a so-called coupled scheduling policy, which is a relaxation of strict gang scheduling, to concurrently schedule these tasks. We propose a technique to model coupled scheduling in (C)SDF graphs. Under our scheduling policies, we also design an admission controller to guarantee the throughput requirements of running applications. To verify the approach, we have implemented a simulation system to run DVB-SH and DVB-T concurrently and independently.
Wei Tong is a Ph.D candidate at Eindhoven University of Technology and is working closely with industrial partner ST-Ericsson. His research focuses on hard real-time scheduling in wireless communication systems, code generation and tasks level parallelization. From 2009 to 2011, he was a design engineer at ASML Netherlands, responsible for software design for complex systems. He received a Master degree in Embedded Systems in 2009 from Eindhoven University of technology. He also holds a BSc degree from Xi’an Jiaotong University.