【06-19】SKLCS Seminar on “Functional Verification in RTL Models using Concolic Testing”

Title: Functional Verification in RTL Models using Concolic Testing
Speaker: Dr. Yangdi Lyu (吕杨迪,Hong Kong University of Science and Technology,Guangzhou)
Time: 6月19日(周一),10:00am
Venue: 线下:中科院软件所5号楼三层334报告厅
Abstract:  Functional verification is one of the most complex stages in chip design. Early detection of bugs at the RTL stage can effectively avoid huge economic losses and reduce time-to-market. Common industry practice runs millions of random or constrained-random tests to cover most functional scenarios quickly. However, it is not always possible to cover all scenarios using these tests. Formal methods, such as model checking, can cover specific scenarios directly but suffer from state explosion for large designs. Concolic testing, as a semi-formal method, combines the advantages of simulation and formal methods to cover targets efficiently. This report briefly reviews the challenges in functional verification, compares several common testing methods, and introduces the semi-formal method studied by our group.
Bio: Yangdi Lyu is an Assistant Professor in the Thrust of Microelectronics of the Function Hub at the Hong Kong University of Science and Technology (Guangzhou), China. He received his B.E. from Tsinghua University in 2011, and Ph.D. from the University of Florida in 2020. His research has mainly focused on designing novel test methodologies to ensure the correctness, trust and security in computing systems, including electronic design automation (EDA), automated test generation, hardware security and trust. His research has resulted in 10+ publications in peer-reviewed journals and premier conferences, including IEEE Transactions on Computers, IEEE Transactions on CAD, and Design Automation and Test in Europe (DATE). His research has been recognized by several awards including Best Poster (Most Popular) Award at ACM SIGDA Student Research Forum at ASP-DAC and nomination for Best Paper Award in DATE 2019.