CONFERENCE PROGRAM
| Day 1: 4 September 2018 | |
|---|---|
| 8:30–09:00 | CONFESTA Opening |
| 09:00–10:00 | CONFESTA Joint Invited Talk Prof. Moshe Vardi, Rice University, USA The Siren Song of Temporal Synthesis |
| 10:00–13:00 | [Possibility to visit talks of other conferences, e.g. CONCUR] |
| 14:30–15:30 | SETTA Opening and Invited Talk 1 Prof. Tao Xie, University of Illinois at Urbana-Champaign, USA Intelligent Software Engineering: Synergy between AI and Software Engineering |
| 15:30–16:00 | Session 1 - Software Assurance | 15:30–16:00 | : Automatic Support of the Generation and Maintenance of Assurance Cases |
| 16:00–16:30 | Coffee Break |
| 16:30–17:30 | Session 2 - Refinement | 16:30–17:00 | : Correct-by-construction Implementation of Runtime Monitors Using Stepwise Refinement |
| 17:00–17:30 | : Identifying Microservices Using Functional Decomposition |
| Day 2: 5 September 2018 | |
| 08:30– 09:30 | [Possibility to visit CONCUR Keynote 1] |
| 09:30–11:00 | Session 3 - Verification | 09:30–10:00 | : Robust Non-termination Analysis of Numerical Software |
| 10:00–10:30 | : Developing GUI Applications in a Verified Setting |
| 10:30–11:00 | : Interleaving-tree Based Fine-grained Linearizability Fault Localization |
| 11:00–11:30 | Coffee break |
| 11:30– | Lunch/Excursion/Banquet |
| Day 3: 6 September 2018 | |
| 09:00–10:00 |
Invited Talk 2 Prof. Hongseok Yang, KAIST, Korea Formal Semantics of Probabilistic Programming Languages: Issues, Results and Opportunities |
| 10:00–11:00 | Session 4 - Miscellaneous (Short Presentations) |
| 10:00–10:20 | : Improvement in JavaMOP by Simplifying Büchi Automaton |
| 10:20–10:40 | : Developing a New Language to Construct Algebraic Hierarchies for Event-B |
| 10:40–11:00 | : Towards the Existential Control of Boolean Networks: A Preliminary Report |
| 11:00–11:30 | Coffee Break |
| 11:30–13:00 | Session 5 - Timing and Scheduling |
| 12:30–13:00 | : Mixed-Criticality Scheduling with Limited HI-Criticality Behaviors |
| 12:00–12:30 | : Probabilistic Analysis of Timing Constraints in Autonomous Automotive Systems using Simulink Design Verifier |
| 11:30–12:00 | : Statistical Model Checking of Response Times for Different System Deployments |
Image from